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I need some assistance with these assignment. synchronized access to shared memory in a multi core computer Thank you in advance for the help! Multi-Core Processors (CMPs) could be broadly classified as Uniform Memory Access (UMA) processors in which all the CPUs are able to access all the memory with no specific preference or Non-Uniform Memory Access (NUMA) processors, where each CPU may have its own special memory area. A system may maintain memory consistency using hardware or using a combination of hardware and software techniques. Hardware can provide a particular memory ordering guarantee, (hardware will maintain the sequential nature of program memory accesses), while software can be used supplement hardware-provided memory ordering by forcing additional ordering restrictions at desired times. The memory ordering scheme implemented is a design choice involving a tradeoff between hardware complexity, software complexity, and the desired ability to cache and buffer data.

Refer Diagram “NUMA Architecture.” (Watson, n.d., p. 4) In NUMA architecture a processor can access its own local memory faster than non-local memory that is, memory local to another processor or memory shared between processors. In this type, all the MPs may or may not be of similar capacity (Asymmetric Multi-Processing). Communication between processors is often based on the use of shared memory between those processors. An ‘Inter-Process Interrupt’ (IPI) allows CPUs to generate notifications to other CPUs to invalidate entries for a shared region or to request termination.

Refer Diagram “UMA Architecture.” (Watson, n.d., p. 3) When multiple processors can access the same shared memory, the MP system has to make sure that the ordering of memory access from one processor is made visible to the other processors.

One way to achieve ‘Cache Coherence’ in an MP environment would be by using the ‘Fencing’ technique. Refer to Diagram ‘MFDA and MFDR Instruction” (Mittal, 1997, p. 26). In this technique, the MP system (11) access and release of shared memory space (15) are done using two special instructions – MFDA and MFDR. The Memory Fence Directional – Acquire (MFDA) (16) instruction locks the specified area from being accessed by other processors. Once the operation is over and data can be released, the Memory Fence Directional – Release (MFDR) (17) instruction is issued. Since an MFDA instruction ‘locks’ the shared data until its use is over and an MFDR instruction is issued, it ensures that no two simultaneous accesses to the shared memory space take place and hence, ‘Cache Coherence’ is always maintained in the shared memory space.

To achieve ‘Synchronized’ access to multiple threads in an MP system, not just ‘Cache Coherence’ but also ‘Access Ordering Control’ or the order in which data is accessed is very important esp. when two accesses have to be done in a particular sequence. The various ‘Memory Consistency Models’ proposed are Sequential consistency, Processor consistency and Weak consistency.

As defined by ‘Lamport’ “A system is ‘Sequentially Consistent’ if the result of any execution is the same as if the operations of all the processes were executed in some sequential order, and the operations of each individual processor appear in this sequence in the order specified by its program” (as cited in Gharachorloo, Lenoski, Laudon, Gibbons, Gupta, Hennessy, n.d., p. 2). Refer Diagram “Sequential Consistency” (Mittal, 1997, p. 27).